During tours of chip fabrication, there is a specific point at which the guide stops discussing figures and just adds, in a hushed voice, “this is where things get strange.” That moment comes early, at two nanometers. At a scale where the standard principles of electricity begin to bend toward the rules of quantum physics, the gates governing electron flow decrease to about ten atoms across. These days, electrons don’t always remain in their designated locations. They leak.
The current state of TSMC’s newest node is entirely due to the leakage issue. FinFET transistors, which wrap the gate around three sides of a silicon channel, performed satisfactorily for almost twenty years. However, as features got this little, three sides were no longer sufficient. N2 entirely wraps the gate around stacked horizontal nanosheets in place of that structure, which is known as Gate-All-Around. It sounds like a little adjustment to geometry. In reality, it’s the difference between a faucet that leaks and one that turns off.
Late last year, TSMC discreetly started mass production on this node at Fab 22, a facility close to Kaohsiung rather than the flagship R&D campus that receives the most of media attention. That decision, a significant technological change occurring at a secondary location rather than with much fanfare at headquarters, has an almost anticlimactic quality. However, it follows the company’s pattern. Before releasing press releases, TSMC usually lets output speak. In this case, the output has been telling a pretty compelling story, with yield figures reportedly rising into the 65 to 80 percent range in a matter of months—numbers that would have seemed optimistic for a first-generation architecture this complicated.
N2 claims a speed increase of 10 to 15 percent at the same power draw or a power reduction of 25 to 30 percent at the same speed as compared to the outgoing 3-nanometer node. Additionally, transistor density increases by about 15%. In isolation, none of those figures sound dramatic. However, when stacked across billions of transistors on a single device, they result in actual variations in the lifespan of a phone battery or the amount of heat that a data center rack must dissipate.
The story’s financial aspect appears to be receiving less attention than it merits. According to reports, the cost of the wafers on this node is close to $30,000 per unit, which is a significant increase above 3-nanometer pricing. This charge is transmitted up the supply chain until it ends up in the retail price of a device or the margin of a cloud provider. It is reasonable to wonder how equitably this technology actually reaches the rest of the business in its first year given that Apple has apparently locked up a sizable portion of early capacity.
The durability of these chips after a few years of operation in real devices as opposed to a lab bench is less certain. On paper, nanosheet transistors are good at handling leakage, and TSMC’s additional capacitor technology aids in stabilizing voltage across increasingly congested wire.
However, everyone, including TSMC, is unfamiliar with two nanometers, and long-term reliability data is just not yet available at scale. With billions of dollars and a good number of assumptions hanging on the outcome, it’s difficult to ignore the fact that the industry is, in a sense, conducting a live experiment on the physics of very small things. The early indicators appear truly encouraging. No one, even TSMC, has a complete response to the question of whether that holds up five years into deployment.
