The motherboard inside nearly every AI server constructed in the last two years hardly looks like something a PC maker from ten years ago would recognize. The tidy rows of DIMM slots that click a memory stick into position are no longer there. They are replaced by something more like to a tiny city of silicon, which is so densely packed and fused that the traditional guidelines for circuit board design are no longer applicable.
That shift was more of a need than a choice. Copper traces imprinted over a fiberglass board connected traditional memory, which was positioned a few inches away from the processor. Because data didn’t have to move quickly, it functioned well for decades. AI workloads disproved that presumption. Because of the speed at which modern GPUs process data, memory that is only a few centimeters away begins to electrically seem to be on the opposite side of the room.
That is resolved by high-bandwidth memory, which doesn’t even sit on the board. Rather, DRAM dies are positioned next to the processor atop a silicon interposer, a specialized layer of silicon that functions more like a precision-etched bridge than a circuit board, after being stacked vertically and connected by tiny Through-Silicon Vias. At Hot Chips 2026, SK Hynix went into great detail about this, describing stacks up to sixteen layers high that communicate with the processor over 1024 input-output channels crammed into a fingernail-sized space. Until you see a die pictures of it, it’s a truly bizarre feat of engineering.
From there, the bodily effects spread. Because the RAM is fused to the package before it ever reaches a server rack, there are no upgrade paths or slots to swap. Once-inch-long traces now barely measure fractions of a millimeter, and this reduction is necessary to maintain signal integrity at terabyte-per-second speeds. Because the massive interposers needed to house both CPU and memory are prone to bending slightly during assembly, warpage becomes a serious yield risk that can subtly spoil an otherwise flawless batch.
Delivery of power becomes a headache in and of itself. Large, fast-switching currents are pulled by a 1024-bit or wider bus, and routing that safely necessitates dense power grids integrated into the package rather than the surrounding board. Heat exacerbates the issue because stacked DRAM is located adjacent to a heated logic die with very little space for the heat to escape. In order to handle it, data center engineers have relied on liquid cooling and vapor chambers, which would have looked overkill for memory only a few product cycles ago.
This is not free, and the expense extends far beyond the server room. The predominant technique for constructing these interposers, TSMC’s CoWoS packaging, has been operating at full capacity for what seems like the whole year, with growth finding it difficult to meet the demand for AI. In late 2025, industrial focus turned to HBM production, which contributed to a notable increase in consumer DDR5 costs. The repercussions of a data center memory shortage are felt by gamers and laptop customers in a strange, almost indirect way, but it seems like things will only get worse before they get better.
It is still unclear if conventional board-level memory design will be used in high-performance computing at all. In regular laptops and desktop computers, where cost is a major factor, it is obviously not going anywhere. However, in the world of chasing AI throughput, the motherboard as most engineers know it—flat, routed, upgradeable—becomes more and more like a design from a slower period, one that is being discreetly removed wherever bandwidth truly matters.
